This commit is contained in:
luboslenco
2025-03-18 16:04:16 +01:00
parent e0588a028c
commit 9d2f93ff45
9 changed files with 1254 additions and 1513 deletions
File diff suppressed because it is too large Load Diff
+13 -57
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@@ -3,12 +3,24 @@
#include <stdbool.h> #include <stdbool.h>
#include <stdint.h> #include <stdint.h>
#define QUEUE_SLOT_COUNT 2
#define IRON_INTERNAL_G5_TEXTURE_COUNT 16
struct ID3D12CommandAllocator; struct ID3D12CommandAllocator;
struct ID3D12GraphicsCommandList; struct ID3D12GraphicsCommandList;
struct ID3D12Fence; struct ID3D12Fence;
struct ID3D12Resource; struct ID3D12Resource;
struct ID3D12DescriptorHeap; struct ID3D12DescriptorHeap;
struct IDXGISwapChain; struct IDXGISwapChain;
struct ID3D12PipelineState;
struct ID3D12RootSignature;
struct ID3D12StateObject;
struct iron_gpu_pipeline;
struct iron_gpu_texture;
struct iron_gpu_sampler;
struct iron_gpu_shader;
struct iron_gpu_command_list;
struct iron_gpu_buffer;
typedef void *HANDLE; typedef void *HANDLE;
typedef unsigned __int64 UINT64; typedef unsigned __int64 UINT64;
@@ -29,8 +41,6 @@ struct D3D12Rect {
long bottom; long bottom;
}; };
#define QUEUE_SLOT_COUNT 2
struct dx_window { struct dx_window {
struct IDXGISwapChain *swapChain; struct IDXGISwapChain *swapChain;
UINT64 current_fence_value; UINT64 current_fence_value;
@@ -45,12 +55,6 @@ struct dx_window {
bool vsync; bool vsync;
}; };
struct iron_gpu_pipeline;
struct iron_gpu_texture;
struct iron_gpu_sampler;
#define IRON_INTERNAL_G5_TEXTURE_COUNT 16
typedef struct { typedef struct {
struct ID3D12CommandAllocator *_commandAllocator; struct ID3D12CommandAllocator *_commandAllocator;
struct ID3D12GraphicsCommandList *_commandList; struct ID3D12GraphicsCommandList *_commandList;
@@ -72,18 +76,6 @@ typedef struct {
struct ID3D12DescriptorHeap *samplerHeap; struct ID3D12DescriptorHeap *samplerHeap;
} gpu_command_list_impl_t; } gpu_command_list_impl_t;
typedef struct {
uint32_t hash;
uint32_t index;
} iron_internal_hash_index_t;
struct iron_gpu_shader;
struct ID3D12PipelineState;
struct ID3D12GraphicsCommandList;
struct ID3D12RootSignature;
struct ID3D12DescriptorHeap;
typedef struct { typedef struct {
struct ID3D12PipelineState *pso; struct ID3D12PipelineState *pso;
int textures; int textures;
@@ -94,19 +86,8 @@ typedef struct {
uint32_t vertexSize; uint32_t vertexSize;
int fragmentOffset; int fragmentOffset;
uint32_t fragmentSize; uint32_t fragmentSize;
int geometryOffset;
uint32_t geometrySize;
int tessEvalOffset;
uint32_t tessEvalSize;
int tessControlOffset;
uint32_t tessControlSize;
} gpu_constant_location_impl_t; } gpu_constant_location_impl_t;
struct iron_gpu_pipeline;
struct iron_gpu_command_list;
void iron_gpu_internal_setConstants(struct iron_gpu_command_list *commandList, struct iron_gpu_pipeline *pipeline);
typedef struct iron_gpu_sampler_impl { typedef struct iron_gpu_sampler_impl {
struct ID3D12DescriptorHeap *sampler_heap; struct ID3D12DescriptorHeap *sampler_heap;
} gpu_sampler_impl_t; } gpu_sampler_impl_t;
@@ -138,14 +119,6 @@ typedef struct {
int length; int length;
} gpu_shader_impl_t; } gpu_shader_impl_t;
struct ID3D12Resource;
struct ID3D12DescriptorHeap;
struct ID3D12GraphicsCommandList;
typedef struct {
int unit;
} TextureUnit5Impl;
typedef struct { typedef struct {
bool mipmap; bool mipmap;
int stage; int stage;
@@ -157,25 +130,16 @@ typedef struct {
struct ID3D12Resource *renderTarget; struct ID3D12Resource *renderTarget;
struct ID3D12Resource *renderTargetReadback; struct ID3D12Resource *renderTargetReadback;
struct ID3D12DescriptorHeap *renderTargetDescriptorHeap; struct ID3D12DescriptorHeap *renderTargetDescriptorHeap;
// struct ID3D12DescriptorHeap *srvDescriptorHeap;
struct ID3D12DescriptorHeap *depthStencilDescriptorHeap; struct ID3D12DescriptorHeap *depthStencilDescriptorHeap;
struct ID3D12DescriptorHeap *srvDepthDescriptorHeap; struct ID3D12DescriptorHeap *srvDepthDescriptorHeap;
struct ID3D12Resource *depthStencilTexture; struct ID3D12Resource *depthStencilTexture;
struct D3D12Viewport viewport; struct D3D12Viewport viewport;
struct D3D12Rect scissor; struct D3D12Rect scissor;
// int stage;
int stage_depth; int stage_depth;
int framebuffer_index; int framebuffer_index;
} gpu_texture_impl_t; } gpu_texture_impl_t;
struct iron_gpu_texture;
struct iron_gpu_command_list;
void iron_gpu_internal_set_textures(struct iron_gpu_command_list *commandList);
void iron_gpu_internal_texture_set(struct iron_gpu_command_list *commandList, struct iron_gpu_texture *texture, int unit);
struct ID3D12Resource;
struct D3D12VertexBufferView { struct D3D12VertexBufferView {
__int64 BufferLocation; __int64 BufferLocation;
unsigned int SizeInBytes; unsigned int SizeInBytes;
@@ -206,16 +170,8 @@ typedef struct {
struct ID3D12Resource *constant_buffer; struct ID3D12Resource *constant_buffer;
int mySize; int mySize;
} gpu_buffer_impl_t; } gpu_buffer_impl_t;
struct iron_gpu_buffer;
void iron_gpu_internal_index_buffer_upload(struct iron_gpu_buffer *buffer, struct ID3D12GraphicsCommandList *commandList);
struct ID3D12StateObject;
struct ID3D12Resource;
typedef struct { typedef struct {
struct ID3D12StateObject *dxr_state; struct ID3D12StateObject *dxr_state;
struct ID3D12Resource *raygen_shader_table; struct ID3D12Resource *raygen_shader_table;
-5
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@@ -43,11 +43,6 @@ typedef struct {
void *_accelerationStructure; void *_accelerationStructure;
} gpu_raytrace_acceleration_structure_impl_t; } gpu_raytrace_acceleration_structure_impl_t;
typedef struct {
int index;
bool vertex;
} TextureUnit5Impl;
typedef struct { typedef struct {
void *_tex; void *_tex;
void *data; void *data;
-2
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@@ -3106,8 +3106,6 @@ void iron_gpu_texture_destroy(iron_gpu_texture_t *target) {
} }
} }
void iron_gpu_internal_texture_set(iron_gpu_texture_t *texture, int unit) {}
int iron_gpu_texture_stride(iron_gpu_texture_t *texture) { int iron_gpu_texture_stride(iron_gpu_texture_t *texture) {
return texture->impl.stride; return texture->impl.stride;
} }
-5
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@@ -13,11 +13,6 @@ typedef struct {
uint32_t number; uint32_t number;
} iron_internal_named_number; } iron_internal_named_number;
typedef struct {
uint32_t hash;
uint32_t index;
} iron_internal_hash_index_t;
struct indexed_name { struct indexed_name {
uint32_t id; uint32_t id;
char *name; char *name;
+4 -4
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@@ -147,12 +147,12 @@ static bool initDefaultDevice() {
a2_buffer.channel_count = 2; a2_buffer.channel_count = 2;
bufferFrames = 0; bufferFrames = 0;
iron_microsoft_affirm(audioClient->lpVtbl->GetBufferSize(audioClient, &bufferFrames)); audioClient->lpVtbl->GetBufferSize(audioClient, &bufferFrames);
iron_microsoft_affirm(audioClient->lpVtbl->GetService(audioClient, &IID_IAudioRenderClient, (void **)&renderClient)); audioClient->lpVtbl->GetService(audioClient, &IID_IAudioRenderClient, (void **)&renderClient);
bufferEndEvent = CreateEvent(0, FALSE, FALSE, 0); bufferEndEvent = CreateEvent(0, FALSE, FALSE, 0);
iron_microsoft_affirm(audioClient->lpVtbl->SetEventHandle(audioClient, bufferEndEvent)); audioClient->lpVtbl->SetEventHandle(audioClient, bufferEndEvent);
return true; return true;
} }
@@ -277,7 +277,7 @@ void iron_a2_init() {
audioProcessingDoneEvent = CreateEvent(0, FALSE, FALSE, 0); audioProcessingDoneEvent = CreateEvent(0, FALSE, FALSE, 0);
iron_windows_co_initialize(); iron_windows_co_initialize();
iron_microsoft_affirm(CoCreateInstance(&CLSID_MMDeviceEnumerator, NULL, CLSCTX_ALL, &IID_IMMDeviceEnumerator, (void **)&deviceEnumerator)); CoCreateInstance(&CLSID_MMDeviceEnumerator, NULL, CLSCTX_ALL, &IID_IMMDeviceEnumerator, (void **)&deviceEnumerator);
if (initDefaultDevice()) { if (initDefaultDevice()) {
CreateThread(0, 65536, audioThread, NULL, 0, 0); CreateThread(0, 65536, audioThread, NULL, 0, 0);
+1 -30
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@@ -136,35 +136,6 @@ enum tagPOINTER_INPUT_TYPE {
#define S_OK ((HRESULT)0L) #define S_OK ((HRESULT)0L)
static void winerror(HRESULT result) {
LPVOID buffer = NULL;
DWORD dw = GetLastError();
__debugbreak();
if (dw != 0) {
FormatMessageA(FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS, NULL, dw,
MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), (LPSTR)&buffer, 0, NULL);
iron_error("Error: %s", buffer);
}
else {
iron_error("Unknown Windows error, return value was 0x%x.", result);
}
}
void iron_microsoft_affirm(HRESULT result) {
if (result != S_OK) {
winerror(result);
}
}
void iron_microsoft_affirm_message(HRESULT result, const char *format, ...) {
}
void iron_microsoft_format(const char *format, va_list args, wchar_t *buffer) { void iron_microsoft_format(const char *format, va_list args, wchar_t *buffer) {
char cbuffer[4096]; char cbuffer[4096];
vsprintf(cbuffer, format, args); vsprintf(cbuffer, format, args);
@@ -1552,7 +1523,7 @@ static bool co_initialized = false;
void iron_windows_co_initialize(void) { void iron_windows_co_initialize(void) {
if (!co_initialized) { if (!co_initialized) {
iron_microsoft_affirm(CoInitializeEx(0, COINIT_MULTITHREADED)); CoInitializeEx(0, COINIT_MULTITHREADED);
co_initialized = true; co_initialized = true;
} }
} }
-2
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@@ -7,8 +7,6 @@ typedef long HRESULT;
struct HMONITOR__; struct HMONITOR__;
struct HWND__; struct HWND__;
void iron_microsoft_affirm(HRESULT result);
void iron_microsoft_affirm_message(HRESULT result, const char *format, ...);
void iron_microsoft_format(const char *format, va_list args, wchar_t *buffer); void iron_microsoft_format(const char *format, va_list args, wchar_t *buffer);
int iron_windows_get_display_for_monitor(struct HMONITOR__ *monitor); int iron_windows_get_display_for_monitor(struct HMONITOR__ *monitor);
+4 -4
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@@ -51,7 +51,7 @@ typedef struct iron_gpu_texture {
gpu_texture_impl_t impl; gpu_texture_impl_t impl;
} iron_gpu_texture_t; } iron_gpu_texture_t;
typedef struct gpu_buffer { typedef struct iron_gpu_buffer {
int myCount; int myCount;
uint8_t *data; uint8_t *data;
gpu_buffer_impl_t impl; gpu_buffer_impl_t impl;
@@ -414,11 +414,11 @@ void iron_gpu_command_list_set_pipeline(iron_gpu_command_list_t *list, struct ir
void iron_gpu_command_list_set_vertex_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer); void iron_gpu_command_list_set_vertex_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer);
void iron_gpu_command_list_set_index_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer); void iron_gpu_command_list_set_index_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer);
void iron_gpu_command_list_set_render_targets(iron_gpu_command_list_t *list, struct iron_gpu_texture **targets, int count); void iron_gpu_command_list_set_render_targets(iron_gpu_command_list_t *list, struct iron_gpu_texture **targets, int count);
void iron_gpu_command_list_upload_index_buffer(iron_gpu_command_list_t *list, struct iron_gpu_buffer *buffer); void iron_gpu_command_list_upload_index_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer);
void iron_gpu_command_list_upload_vertex_buffer(iron_gpu_command_list_t *list, struct iron_gpu_buffer *buffer); void iron_gpu_command_list_upload_vertex_buffer(iron_gpu_command_list_t *list, struct iron_gpu_buffer *buffer);
void iron_gpu_command_list_upload_texture(iron_gpu_command_list_t *list, struct iron_gpu_texture *texture); void iron_gpu_command_list_upload_texture(iron_gpu_command_list_t *list, struct iron_gpu_texture *texture);
void iron_gpu_command_list_set_vertex_constant_buffer(iron_gpu_command_list_t *list, struct iron_gpu_buffer *buffer, int offset, size_t size); void iron_gpu_command_list_set_vertex_constant_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer, int offset, size_t size);
void iron_gpu_command_list_set_fragment_constant_buffer(iron_gpu_command_list_t *list, struct iron_gpu_buffer *buffer, int offset, size_t size); void iron_gpu_command_list_set_fragment_constant_buffer(iron_gpu_command_list_t *list, iron_gpu_buffer_t *buffer, int offset, size_t size);
void iron_gpu_command_list_execute(iron_gpu_command_list_t *list); void iron_gpu_command_list_execute(iron_gpu_command_list_t *list);
void iron_gpu_command_list_wait_for_execution_to_finish(iron_gpu_command_list_t *list); void iron_gpu_command_list_wait_for_execution_to_finish(iron_gpu_command_list_t *list);
void iron_gpu_command_list_get_render_target_pixels(iron_gpu_command_list_t *list, struct iron_gpu_texture *render_target, uint8_t *data); void iron_gpu_command_list_get_render_target_pixels(iron_gpu_command_list_t *list, struct iron_gpu_texture *render_target, uint8_t *data);